1. Field of the Invention
The invention relates to a memory cell process and, in particular, to a method for manufacturing split-gate flash memory cells.
2. Description of the Prior Art
A method for manufacturing electrically erasable programmable read-only memories (EEPROM) is disclosed by Naruke et al. in "A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on its Source Side" (Technical Digest of IEEE Electron Device Meeting in 1988). Referring to FIGS. 1A and 1B, a first poly-silicon layer and a second poly-silicon layer are formed as a floating gate 10 and a control gate 12, respectively. Next, a third poly-silicon layer is deposited; then, an etch-back technique is utilized to form a selection gate 14 wherein the height of the selection gate 14, defined by the height of the floating gate 10 and control gate 12, is about 0.4 .mu.m. In addition, since etch-back is used in the above process, the selection gate 14 must be parallel to the control gate 12.
The disadvantages of the above-mentioned conventional process are that the selection gate and control gate which are parallel with each other take up too much space and the length of the selection gate is fixed, so that the characteristics of the memory can not be effectively adjusted. Solutions for overcoming these disadvantages are described in "A novel high density contactless flash memory array using split-gate source-side injection cell for 5V-only application" by Y. Ma at a symposium on VLSI Technology in 1994. As shown in FIG. 2, a high-density memory array and high access efficiency can be obtained by forming a parallel selection gate 22. However, due to limitations in the precision of the photolithography used to form the above-mentioned split-gate structure, the length of the selection gate 22 must be increased, thereby consuming a larger amount of space on the substrate and preventing a drain 24 and source 26 from being formed using separate and different implantations selected on the basis of desired and possibly different characteristics.